Layout driven FPGA packing algorithm for performance optimization

Layout driven FPGA packing algorithm for performance optimization

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, b...

Layout Driven Logic Synthesis and Optimization techniques for FPGA

Empirical Performance-Model Driven Data Layout Optimization

Empirical optimizers like ATLAS have been very effective in optimizing computational kernels in libraries. The best choice of parameters such as tile size and degree of loop unrolling is determined by executing different versions of the computation. In contrast, optimizing compilers use a model-driven approach to program transformation. While the model-driven approach of optimizing compilers is...

Layout-driven Logic Optimization

With the advent of deep sub-microntechnologies,interconnectloads and delays are becoming dominant. Consequently, the currently used design ow of iterativelyperforming logic synthesis with statistical wire-load models, doing placement & routing, extracting par-asitics, and using them back in the synthesis tool runs into serious timing convergence problems. Layout-driven synthesis has become the ...

an adapted harmony search based algorithm for facility layout optimization

this paper presents a strategy for using harmony search algorithm in facility layout optimization problems. in this paper an adapted harmony search algorithm is developed for solving facility layout optimization problems. this method finds an optimal facility arrangement in an existing layout. two real-world case studies are employed to demonstrate the efficiency of this model. a comparison is ...